1. Field of the Invention
This invention relates to the field of computer system architecture. More particularly, this invention relates to configuring peripheral components coupled to multiple peripheral component buses of a computer system.
2. Background
In a computer system, peripheral components such as disc drive controllers, network controllers, and graphics controllers, may be coupled to peripheral component buses separate from a main memory bus. A system may have one peripheral component bus for communication among all peripheral components, or may disperse the peripheral components among multiple peripheral component buses. A bridge circuit is used for communication between buses; either between a main memory bus and a peripheral component bus, or between two peripheral component buses.
There are several reasons a system might employ multiple peripheral component buses. For example, it may be desirable to isolate slower speed devices from higher bandwidth buses and peripherals. Also, an intelligent peripheral component may have a local peripheral component bus. Moreover, the system may have more peripheral components than can be reliably placed on one peripheral component bus, due to electrical loading effects.
A system with multiple peripheral component buses can be arranged in a hierarchical fashion, with the top level comprising the main memory bus. A bridge circuit is used to couple the main memory bus to a peripheral component bus on the second level. A second level peripheral component bus can be coupled through another bridge circuit to another peripheral component bus on the third level, and so on. Also, there may be more than one peripheral component bus on a given level, which means that there may be more than one bridge circuit coupled to a given bus.
To allow flexibility in coupling a variety of peripheral components to the peripheral component buses, it is desirable that a CPU be able to transfer configuration data to and from each of the peripheral components. This capability allows the CPU to control the address and I/O spaces of the peripheral components. In past systems, portions of memory or I/O address space have been dedicated to configuration areas on a component by component basis. However, these past methods reduce flexibility in placement of peripheral components on the peripheral component buses, since the dedicated configuration areas are likely to overlap.
As will be described, the present method and apparatus provides a configuration space enable/disable mechanism for transferring configuration data to and from peripheral components coupled to one or more peripheral component buses. The configuration space enable/disable mechanism allows flexible placement of peripheral components on the peripheral component buses.